The PowerQUICC III is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications, excelling particularly in communications and networking products. Freescale's PowerQUICC III processor family is the next generation of integrated communications processors. The PowerQUICC III provides higher performance in all areas of device operation, including greater flexibility, extended capabilities, and higher integration.
Freescale's leading PowerQUICC III architecture integrates two processing blocks. One block is a high-performance embedded e500 core. With 256 KB of level 2 cache, the e500 core is built on Power Architecture® technology and provides unprecedented levels of hardware and software debugging support. The second block is the communications processor module (CPM). The CPM of the PowerQUICC III can support three fast serial communications controllers (FCCs), two multichannel controllers (MCCs), four serial communications controllers (SCCs), one serial peripheral interface (SPI) and one I²C interface.
The PowerQUICC III also offers two integrated 10/100/1000 Ethernet controllers, a DDR SDRAM memory controller, a 64-bit PCI-X/PCI controller, and a RapidIO® interconnect. This high level of integration helps simplify board design and offers significant bandwidth and performance for high-end control-plane and data-plane applications.
Features
Embedded e500 compatible core available from 600 MHz up to 1 GHz
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32-bit, dual-issue, superscalar, seven-stage pipeline
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1850 MIPS at 800 MHz (est. Dhrystone 2.1)
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32 KB L1 data and 32 KB L1 instruction cache with line locking support
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256 KB on-chip L2 cache with direct mapped capability
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Enhanced hardware and software debug support
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Memory management unit (MMU)
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SIMD extension with single precision floating point
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High-performance RISC CPM available at up to 333 MHz
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CPM software compatibility with previous families
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Greater than 1 Gbps aggregate CPM bandwidth
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32 KB of dual-port RAM
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128 KB of ROM + 32 KB of RAM for protocol microcode storage
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Two UTOPIA Level II master/slave ports with multi-PHY support (one can be 16-bit)
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Three MII interfaces
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Eight TDM interfaces (T1/E1), two TDM ports that can be interfaced with T3/E3
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Four SCCs supporting HDLC and SDLC, HDLC bus, UART, Transparent, BISYNC
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Three FCCs supporting:
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Up to 155 Mbps ATM SAR-AAL0, AAL1, AAL2, AAL3/4, AAL5
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10/100 Mbps Ethernet (up to three) IEEE® 802.3X
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45 Mbps HDLC/transparent (up to three)
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Two MCCs each supporting 128 full-duplex, 64 kbps, HDLC lines for a total of 256 channels
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ATM transmission convergence layer capabilities (8 channels)
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Integrated inverse multiplexing for ATM (IMA) functionality
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Two triple-speed Ethernet controllers (TSECs) supporting 10/100/1000 Mbps Ethernet (IEEE 802.3, 802.3u, 802.3x, 802.3z, and 802.3ac compliant) with two GMII/TBI/RGMII interfaces
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166 MHz, 64-bit, 2.5V I/O, DDR SDRAM memory controller with full ECC support
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500 MHz, 8-bit, LVDS I/O, RapidIO controller
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133 MHz, 64-bit, 3.3V I/O, PCI-X 1.0a/PCI 2.2 bus controller
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166 MHz, 32-bit, 3.3V I/O, local bus with memory controller
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Integrated four-channel DMA controller
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Interrupt contr