The Qorivva MPC564xS family is the next generation platform to follow the highly successful MPC560xS family designed to meet the needs of automotive instrument cluster market. The platform architecture includes on-chip display control units that directly drives the TFT displays.
Further, there is an industry standard graphics accelerator available to help drive sophisticated graphics such as simulated instrument cluster needles or image warping for heads-up displays. In addition to large built in memory, Quad SPI and DDR interfaces facilitate the possibility of accessing additional external memory. Finally, the Qorivva MPC564xS products offer code compatibility to customers already developing applications in the MPC560xS environment.
Features
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Dual-issue, 32-bit Power Architecture Book E compliant CPU core complex (e200z4d) Memory management unit and 4 KB instruction cache
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Variable length encoding (VLE) instruction set enables significant code size reduction over conventional Book E-compliant code
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Up to 2 MB on-chip flash with flash controller
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Separate 4 x 16 KB flash block for EEPROM emulation
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Up to 64 KB on-chip SRAM with ECC
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Up to 1 MB on-chip graphics SRAM (no ECC)
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Two TFT displays up to WVGA resolution parallel data interface (PDI) for digital video input
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Sound generation and playback using PCM or DDS sources with 4-channel mixer and PWM or I2S outputs
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Stepper motor drivers with stepper stall detect for up to six gauges
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