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PC47PQ35/35Z-12

厂商:
TDK
类别:
软磁铁氧体
包装:
-
封装:
-
无铅情况/ROHS:
-
描述:
-

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  • 参数
  • 描述
  • 文档
参数 数值
初始磁导率 μi-Typ 2500
TDK材质名称 PC47
是否无铅 Yes
居里温度 Tc-Min 230Cel
软磁铁氧体材料 Mn-Zn
磁芯形状 PQ
最少包装数-Nom 70Pcs
最少供货数-Nom 0Pcs
饱和磁通密度 Bs 测定条件 at.100 degrees Celsius
饱和磁通密度 Bs-Typ 420 mT
重量-Nom 0g

The MPC862 Quad Integrated Communications Controller (PowerQUICCTM ) is a versatile one-chip integrated microprocesor and peripheral combination that can be used in a variety of controller applications. It particularly excels in both communications and networking systems.

The MPC862 is a Power Architecture-based derivative of Freescale Semiconductor's MC68360 Quad Integrated Communications Controller (QUICC™). The embedded CPU on the MPC862 is a 32-bit processor (the MPC8xx core) that is built on Power Architecture and incorporates memory management units (MMUs) and instruction and data caches. The communications processor module (CPM) from the MC68360 QUICC has been enhanced by the addition of the inter-integrated controller (I2C) channel. The memory controller has been enhanced, enabling the MPC862 to support any type of memory, including high-performance memories and new types of DRAMs. A PCMCIA socket controller supports up to two sockets. A real-time clock has also been integrated.

View Block Diagram

Features

  • Embedded MPC8xx core
  • Single-issue, 32-bit version of the core (compatible with Power Architecture technology) with 32, 32-bit general-prupose registers (GPRs)
  • The MPC862 provides enhanced ATM functionality over that of the MPC860SAR. The MPC862 adds major new features available in "enhanced SAR" (ESAR) mode, including the following:
    • Multiple APC priority levels available to support a range of traffic pace requirements
    • Port-to-port switching capability without the need for RAM-based microcode
    • Simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability
    • Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode
    • Supports full-duplex UTOPIA master (ATM side) operation using a "split" bus
  • Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
  • 32 address lines
  • Complete static design
  • Memory controller (eight banks)
  • General-purpose timers
  • Fast Ethernet controller (FEC)
  • System integration unit (SIU)
  • Interrupts
  • Communications processor module (CPM)
  • Four baud rate generators
  • Four SCCs (serial communication controllers)
  • Two SMCs (serial management channels)
  • One SPI (serial peripheral interface)
  • One I2C (inter-integrated circuit) port
  • Time-slot assigner (TSA)
  • Parallel interface port (PIP)
  • PCMCIA interface
  • Low power support
  • Debug interface
  • 3.3 V operation with 5-V TTL compatibility
  • 357-pin ball grid array (BGA) package

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