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MC68MH360AI25VL

厂商:
Freescale
类别:
ColdFire/68K
包装:
-
封装:
FQFP 240 32*32*3.4P0.5
无铅情况/ROHS:
无铅
描述:
QUICC, 2SMC, 1SPI

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参数 数值
Export Control Classification Number (US) 3A991
Floor Life 168 HOURS
Halogen Free Yes
Harmonized Tariff (US) Disclaimer 8542.31.0000
Tape & Reel No
UL94 (plastics flammability test) V0: burning stops within 10 seconds on a vertical specimen; no drips allowed
Device Weight (g) 7.34990
Life Cycle Description (code) NOT RECOMMENDED(DECLINING)
Package Description and Mechanical Drawing FQFP 240 32*32*3.4P0.5
Package Material Plastic
Debug Features JTAG
Internal RAM (kByte) 2.5
REACH SVHC Freescale REACH Statement
Part Number MC68MH360AI25VL
I/O Operating Voltage (Max) (V) 3.3
Micron Size (μm) .57
POQ Container BOX
Description QUICC, 2SMC, 1SPI
Maximum Time at Peak Temperature (s) 40
MPQ Container TRAY
Status Not Recommended for New Design
2nd Level Interconnect e3
Minimum Package Quantity (MPQ) 24
Device Sample Availability 28 Apr 2005
Preferred Order Quantity (POQ) 240
Serial Interface - Number of Interfaces 4 / 2 / 1
Budgetary Price($US) 100 @ $56.15 each
Bus Frequency (Max) (MHz) 25
Mounting Style Surface Mount
Communication Protocol X.21 / V.14 / UART / Transparent / SS7 / Profibus / HDLC / Ethernet / DDCMP / BISYNC / AppleTalk
Moisture Sensitivity Level (MSL) 3
Material Type Tested Packaged Device
Number of Reflow Cycles 3
Peak Package Body Temperature (PPT)(°C) 260
Sample Exception Availability N
Package Length (nominal) (mm) 32.000
Package Thickness (nominal) (mm) 4.100
Package Width (nominal) (mm) 32.000
Application/Qualification Tier COMMERCIAL, INDUSTRIAL
Device Production Availability 28 Apr 2005
Material Composition Declaration (MCD) Download MCD Report
Pin/Lead/Ball Count 240
RoHS Certificate of Analysis (CoA) Contact Us
Serial Interface - Type SCC / SMC / SPI

The MC68302 is a versatile one-chip processor that incorporates the main building blocks needed for the design of a wide variety of networking and communications products.

The MC68302 was the first device to offer the benefits of a closely coupled, industry-standard, MC68000/MC68008 microprocessor core and a flexible communications architecture. This multi-channel communications device may be configured to support a number of popular industry-standard interfaces, including those for the Integrated Services Digital Network (ISDN) basic rate and terminal adapter applications. Through a combination of architectural and programmable features, concurrent operation of different protocols is easily achieved using the MC68302. Data concentrators, modems, line cards, bridges, and gateways are examples of other suitable applications for this versatile device.

The MC68302 is an HCMOS device consisting of an MC68000/MC68008 microprocessor core, a system integration block (SIB), and a communications processor (CP).

This device is still recommended for new designs.


Features

  • MC68000/MC68008 Microprocessor Core
  • Efficient architecture involves a separate RISC processor for handling communications
  • Three Serial Communications Controllers (SCCs)
  • Support for HDLC/SDLC, Bisync, UART, DDCMP, and Totally Transparent protocols.
  • Two Serial Management Controllers (SMCs) for IDL and GCI Channel.
  • Available at 16, 20, 25, and 33 MHz in three different Thin Quad Flat Pack Packages.
  • Strong 3rd Party tools support.
Typical Applications
  • ISDN equipment
  • Data Concentrators
  • Modems
  • Line Cards
  • Network Bridges
  • Gateways
  • MC68000/MC68008 Microprocessor Core (May be disabled to use the IMP as a peripheral)
  • SIB Including:
    • Independent Direct Memory Access (IDMA) Controller
    • Interrupt controller with two modes of operation
    • Parallel I/O ports, some with interrupt capability
    • On-Chip 1152-bytes of dual-port RAM
    • Three timers, with a software watchdog timer
    • Four programmable chip-select lines with wait-state logic
    • Programmable address mapping of dual-port RAM and IMP registers
  • On-Chip clock generator with an output clock signal
  • System Control
    • Bus arbitration logic with low interrupt latency support
    • System control register
    • Hardware watchdog for monitoring bus activity
    • Low power (Standby) modes
    • Disable CPU logic (M68000)
    • Freeze control for debugging selected on-chip peripherals
    • DRAM refresh controller
  • CP Including:
    • Main controller (RISC Processor)
    • Three full-duplex Serial Communication/Controllers with the following protocols:
      • HDLC/SDLC
      • Bisync
      • UART
      • DDCMP
      • Totally Transparent
      • V.110
    • Six serial DMA channels dedicated to the three SOCs
    • Capability to send/receive up to eight buffers/frames without M68000 core intervention
    • Flexible physical interface accessible by SCCs for Inter-chip Digital Link (IDL), General Circuit Interface (GCI).
    • Pulse Code Modulation (PCM), and Non-multiplexed Serial Interface (NMSI) Operation.
Application Notes
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