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ATXMEGA64D3-AU

厂商:
Atmel
类别:
ATxmega系列单片机
包装:
Tray
封装:
TQFP 64A 64
无铅情况/ROHS:
有铅
描述:
8/16-bit AVR XMEGA D3 Microcontro...

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  • 参数
  • 描述
参数 数值
系列 AVR® XMEGA
核心处理器 AVR
芯体尺寸 8/16-Bit
速度 32MHz
RAM容量 4K x 8
程序存储器类型 FLASH
程序存储器容量 64KB (64K x 8)
EEPROM 大小 4K x 8
输入/输出数 50
振荡器型 Internal
数据转换器 A/D 16x12b
连通性 I²C, IrDA, SPI, UART/USART
工作电压 1.6 V ~ 3.6 V
工作温度 -40°C ~ 85°C
周边设备 Brown-out Detect/Reset, POR, PWM, WDT
SPI 5
Max I/O Pins 50
CPU 8-bit AVR
Self Program Memory YES
Operating Voltage (Vcc) 1.6 to 3.6
picoPower Yes
EEPROM (Bytes) 2048
Video Decoder No
Flash (Kbytes) 64 Kbytes
SRAM (Kbytes) 4
Temp. Sensor Yes
Input Capture Channels 18
FPU No
Crypto Engine No
Ext Interrupts 50
Analog Comparators 2
Temp. Range (deg C) -40 to 85
Camera Interface No
TWI (I2C) 2
MPU / MMU no / no
ADC Speed (ksps) 200
External Bus Interface 0
Calibrated RC Oscillator Yes
Hardware QTouch Acquisition No
Pin Count 64
Graphic LCD No
32kHz RTC Yes
Max. Operating Frequency 32 MHz
ADC Resolution (bits) 12
Resistive Touch Screen No
DAC Resolution (bits) 0
UART 3
Output Compare channels 18
PWM Channels 18
Timers 5
USB Speed No
I/O Supply Class 1.6 to 3.6
ADC channels 16
# of Touch Channels 16
DRAM Memory No
USB Interface No
NAND Interface No

The high-performance, low-power 8/16-bit AVR XMEGA microcontroller combines 64KB ISP flash memory (4KB boot code section) with read-while-write capabilities, 2KB EEPROM, 4KB SRAM, a four-channel event system, a programmable multi-level interrupt controller, 50 general purpose I/O lines, a 16-bit real time counter, five flexible 16-bit timer/counters with compare modes and PWM, three USARTs, two 2-wire interfaces, two serial peripheral interfaces, one 16-channel/12-bit A/D converter with optional differential input with programmable gain, two analog comparators with window mode, a programmable watchdog timer with separate internal oscillator, accurate internal oscillators with PLL and prescaler, and a programmable brown-out detection. The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging, is available. By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching 1 MIPS per MHz, balancing power consumption and processing speed.

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