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LT1806CS6#TRPBF

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精准放大器
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The MPC8245 Integrated Host Processor fits applications where cost, space, power consumption and performance are critical requirements. This device provides a high level of integration, reducing chip count from five discrete chips to one, thereby significantly reducing system component cost. High integration results in a simplified board design, less power consumption and a faster-time-to-market solution. This cost-effective, general purpose integrated processor targets systems using PCI interfaces in networking infrastructure, telecommunications, and other embedded markets. It can be used for control processing in applications such as routers, switches, network storage applications and image display systems.

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Features

  • 32-bit PCI interface operating at up to 66 MHz
  • Memory controller offering SDRAM support up to 133 MHz operation, support up to 2 GB
  • General Purpose I/O and ROM Interface Support
  • Two-channel DMA controller that supports chaining
  • Messaging unit with I2O messaging support capability
  • Industry-standard I2C interface
  • Programmable interrupt controller with multiple timers and counters
  • 16550 compatible DUART
  • Routers/Switches
  • Multi-channel modems
  • Network storage
  • Image display systems
  • Enterprise I/O processor
  • Internet access device (IAD)
  • Disk controller for RAID systems
  • Copier/printer board control
  • MPC603e processor core
    • High-performance, superscalar processor core
    • Floating-point unit, integer, load/store, system register and branch processing unit
    • 16K instruction cache, 16K data cache
    • Lockable portion of L1 cache
    • Dynamic power management
    • Software-compatible with processors built on Power Architecture technology
  • Memory interface
    • 133 MHz memory bus capability
    • Programmable timing EDO DRAM or SDRAM
    • High-bandwidth bus (32/64-bit data bus) to DRAM
    • Supports one to eight banks of 16-, 64-, 128-, 256-, or 512 Mbit DRAM, and up to four banks of 256-Mbit SDRAM devices
    • Supports 1 Mbyte to 2 Gbyte DRAM memory
    • Contiguous memory mapping
    • 256 Mbytes of ROM space
    • 8-bit, 16-bit, 32-bit, or 64-bit ROM
    • Supports bus-width writes to flash
    • Read-modify-write parity support (selectable)
    • ECC support (selectable)
    • SDRAM, DRAM buffer data-path
    • Error injection/capture on data path
    • LVTTL compatible
    • PortX: 8-, 32- or 64-bit general-purpose I/O port uses ROM controller interface with address strobe
  • 32-bit PCI interface operating up to 66 MHz
    • PCI 2.2 compatible
    • PCI 5.0 V tolerant
    • Support for PCI locked accesses to memory
    • Support for accesses to all PCI address spaces
    • Selectable big- or little-endian operation
    • Store gathering of processor-to-PCI writes and PCI-to-memory writes
    • Memory prefetching of PCI read accesses
    • Parity support (selectable)
    • Selectable hardware-enforced coherency
    • PCI bus arbitration unit (5 request/grant pairs

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